TSMC FinFlex: How Chips are made Worse to get Better
High Yield
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Analysis, commentary and current developments in hardware and tech. Everything silicon.
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A deep-dive into FinDepopulation & TSMCs FinFlex technology. How the height of transistors is keeping Moore's Law alive. Become a supporter on Patreon: https://www.patreon.com/notifications Follow me on Twitter/X: https://x.com/home SemiAnalysis article: https://www.semianalysis.com/p/iedm2022p1 Ken Shirrif's blog: http://www.righto.com/2024/01/intel-386-standard-cells.html 0:00 Intro 0:50 NMOS, PMOS & CMOS Transistors 3:34 3D FinFETs & Transistor Height 6:48 Logic Gates & Standard Cells 9:54 Process Node Cell Libraries 13:31 How Fin Depopulation works 14:48 FinFET Process Node Scaling 18:34 TSMC FinFlex & Standard Cell Height 23:22 The future of chip design
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